Systemverilog Verification -6: Simulation Regions in Detail

Publisher : Ajith Jose

Course Length : 1.5 hour

Course Price : $0

Course Language : English

Description

This Systemverilog course teaches the System-On-Chip design verification used in VLSI industry. It is teaching only a specific topic in SV, the simulation time regions.

While learning SV verification or even after spending years in writing test-benches, it is a hard task for most of the verification engineers to answer anything demanding in depth knowledge in simulation time regions.  Here in this course, this problem is addressed in a simplified manner by explaining every time regions in detail, and connecting different code regions to time regions. You will going through the "Preponed, Active, Reactive, NBA, Observed, Re-Active, Re-Reactive, Re-NBA and Postponed Regions" in Systemverilog one by one.

By taking this course, you will be able to explain what is happening in simulation in each time slot with respect to the code you write. This would be an excellent platform to brush up your SV skills and to address common verification questions confidently.

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